library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity validator is
	port(
		-- inputs:
		d_address_in : in STD_LOGIC_VECTOR (14 DOWNTO 0);
        d_byteenable_in : in STD_LOGIC_VECTOR (3 DOWNTO 0);
        d_read_in : in STD_LOGIC;
        d_write_in : in STD_LOGIC;
        d_writedata_in : in STD_LOGIC_VECTOR (31 DOWNTO 0);
        i_address_in : in STD_LOGIC_VECTOR (14 DOWNTO 0);
        i_read_in : in STD_LOGIC;
		
		d_address_in_0 : in STD_LOGIC_VECTOR (14 DOWNTO 0);
        d_byteenable_in_0 : in STD_LOGIC_VECTOR (3 DOWNTO 0);
        d_read_in_0 : in STD_LOGIC;
        d_write_in_0 : in STD_LOGIC;
        d_writedata_in_0 : in STD_LOGIC_VECTOR (31 DOWNTO 0);
        i_address_in_0 : in STD_LOGIC_VECTOR (14 DOWNTO 0);
        i_read_in_0 : in STD_LOGIC;
			
		d_address_in_1 : in STD_LOGIC_VECTOR (14 DOWNTO 0);
        d_byteenable_in_1 : in STD_LOGIC_VECTOR (3 DOWNTO 0);
        d_read_in_1 : in STD_LOGIC;
        d_write_in_1 : in STD_LOGIC;
        d_writedata_in_1 : in STD_LOGIC_VECTOR (31 DOWNTO 0);
        i_address_in_1 : in STD_LOGIC_VECTOR (14 DOWNTO 0);
        i_read_in_1 : in STD_LOGIC;
			
		d_address_in_2 : in STD_LOGIC_VECTOR (14 DOWNTO 0);
        d_byteenable_in_2 : in STD_LOGIC_VECTOR (3 DOWNTO 0);
        d_read_in_2 : in STD_LOGIC;
        d_write_in_2 : in STD_LOGIC;
        d_writedata_in_2 : in STD_LOGIC_VECTOR (31 DOWNTO 0);
        i_address_in_2 : in STD_LOGIC_VECTOR (14 DOWNTO 0);
        i_read_in_2 : in STD_LOGIC;

		validation_sel : in std_logic_vector (1 downto 0);
		validation_enable : in std_logic;
		
		-- outputs:
		valid : out std_logic
	);
end entity;

architecture behavioral of validator is

begin

	P1 : process (validation_enable, validation_sel, 
				d_address_in, d_byteenable_in, d_read_in, d_write_in, d_writedata_in, i_address_in, i_read_in, 
				d_address_in_0, d_byteenable_in_0, d_read_in_0, d_write_in_0, d_writedata_in_0, i_address_in_0, i_read_in_0, 
				d_address_in_1, d_byteenable_in_1, d_read_in_1, d_write_in_1, d_writedata_in_1, i_address_in_1, i_read_in_1,
				d_address_in_2, d_byteenable_in_2, d_read_in_2, d_write_in_2, d_writedata_in_2, i_address_in_2, i_read_in_2)

	begin
		if validation_enable = '1' then
			case validation_sel is
				when "00" =>
					if d_address_in_0 = d_address_in and d_byteenable_in_0 = d_byteenable_in and d_read_in_0 = d_read_in and d_write_in_0 = d_write_in and d_writedata_in_0 = d_writedata_in and i_address_in_0 = i_address_in and i_read_in_0 = i_read_in then
						valid <= '1';
					else
						valid <= '0';
					end if;
				when "01" =>
					if d_address_in_1 = d_address_in and d_byteenable_in_1 = d_byteenable_in and d_read_in_1 = d_read_in and d_write_in_1 = d_write_in and d_writedata_in_1 = d_writedata_in and i_address_in_1 = i_address_in and i_read_in_1 = i_read_in then
						valid <= '1';
					else
						valid <= '0';
					end if;
				when "10" =>
					if d_address_in_2 = d_address_in and d_byteenable_in_2 = d_byteenable_in and d_read_in_2 = d_read_in and d_write_in_2 = d_write_in and d_writedata_in_2 = d_writedata_in and i_address_in_2 = i_address_in and i_read_in_2 = i_read_in then
						valid <= '1';
					else
						valid <= '0';
					end if;

				when others =>
					valid <= '0';
			end case;
		else
			valid <= '0';
		end if;
	end process;
	
end behavioral;